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1 9-7030; rev 4; 11/14 maxim integrated products, inc. 1 vt1697sb smart slave ic with integrated current and temperature sensors the vt1697sb is a feature-rich smart slave ic designed to work with maxim?s seventh-generation masters to implement a high- density multiphase voltage regulator. up to six smart slave ics, plus a master ic, provide a compact synchronous buck converter that includes accurate individual phase-current and temperature reporting via smbus/pmbus. this smart slave device includes protection circuits for overtemper ature, vx short, all power sup- plies uvlo faults and main power supply ovlo fault. if a fault is detected, the slave ic will immediat ely shut down and send a fault signal to the master ic. monolithic integration and advanced packaging technologies allow practical per-phase, high switchin g frequencies with significantly lower losses than alternative implementations. smart slave devices are designed to support phase-shedding and dcm modes for efficiency optimization over a wide range of load cur- rents. high per-phase current-capability designs with low c out enable a design with fewer phases and a smaller footprint. the vt1697sb is packaged in a qfn package with exposed top- side thermal pads. top-side cooling allows improved heat transfer to ambient and reduces pc board and component temperatures. figure 1: basic application circuit features an d benefits ? increased power density with fewer external components ? monolithic integration for reduced parasitics ? 4-phase scalable architecture compatible with coupled inductors ? 94% peak efficiency ? top-side cooling for improved heat transfer to ambient ? accurate telemetry and monitoring provides real-time reporting of critical parameters ? pmbus compliant interface via master controller for telemetry and power management ? junction temperature monitoring & reporting ? per-phase current reporting ? advanced self-protection features protects system and ic ? overcurrent protection ? overtemperature protection ? boost voltage uvlo ? vx short protection applications ? communication and networking equipment ? servers and storage equipment ? high-current voltage regulators ? networking asics ? fpgas ? microprocessor chipsets ? memory device type operating current input voltage vt1697sb 55a per phase 8.5v to 14.0v control1 i sense 1 i sense 2 i sense 3 v out control2 control6 sense+ sense- t sense 1 t sense 2 t sense 6 svid smbus multiphase master vt1697sbvt1697sb vt1697sb downloaded from: http:///
2 maxim integrated products, inc. vt1697sb ordering information absolute maximum ratings 1 supply voltage (12v) ........................................... -0.3v to 16v supply & input pin voltages (1.8v) .................... -0.3v to 2.5v switching node voltage (vx) dc ........................ -0.3v to 16v switching node voltage (vx) 25ns 2 ..................... -10v to 23v v ddh pin - vx pin differential 25ns 4 .................... -10v to 23v bst pin (bst) dc............................................... -0.3v to 20v bst pin (bst) 25ns ............................................ -6.0v to 27v bst pin - vx pin differential ............................................2.5v operating junction temperature (t j ) ............................ 150c storage temperature range ..........................-65c to 150c peak reflow temperature.............................................. 260c operating ratingsv dd , v cc .......................................................... 1.71v to 1.98v 12v supply (v ddh ) ............................................ 8.5v to 14.0v junction temperature (t j ) ............................... -40c to 125c frequency (fsw).........................................300khz to 1.3mhz thermal ratings vt1697sb ? jc max .................................................0.42c/w note 1: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only; functional operation of the device at these or any other conditi ons beyond those indicated in t he operational sections of the s pecifications is not implied. exposure to absolute maximu m rating conditions for extended periods may affect device reliability. note 2: the 25ns rating is the allowable voltage that the vx node may exc eed the -0.3v to 16v ratings in either positive or negative di rection for up to 25ns per cycle. note 3: these products are completely halogen-free and pb-free, employing special materials sets: molding compounds/die attach material s and 100% matte tin plate including anneal. these products are rohs compliant with an -e3 terminati on finish and are compatible with both snpb and pb- free soldering operations. these products are msl classified at peak reflow te mperatures that meet jedec jstd-020. note 4: the v ddh input pin voltage ac should not exceed 19v ( 25ns). this measurement is taken at the v ddh pin referenced to v ss pin immediately adjacent using a high frequency scope probe with i load at i max . a high-frequency input bypass capacitor must be located less than 60mils (1.524mm) from the v ddh pin and the maxim device per our design guidelines. part number description package drawing number shipping method package marking rohs compliant 3 vt1697sbfqx 55a smart slave device qfn-16 [type g] es ap-2896 2.5ku tape & reel vt1697sbf downloaded from: http:///
3 maxim integrated products, inc. vt1697sb electrical characteristics v dd = v cc = 1.71v - 1.98v, v ddh = 12v. the ? symbol denotes specifications which apply over the following temperature range: t j = 0 to 125c, otherwise specifications are for t j = 25c. the # symbol denotes specifications which apply over the following temperature range: t j = -25 to 125c. symbol parameter conditions min typ max units supply voltages , supply current v dd , v cc bias supply voltage 1.71 1.98 v v ddh power train input voltage 8.5 12.0 14.0 v i cc + i dd 1.8v bias supply current shutdown (see note 1) 0.5 2 a inactive, no switching (see note 2) 3.2 5.0 ma load = 0a, v out = 1.8v, fsw = 1.5mhz 43 61 ma load = 0a, v out = 1.8v, fsw = 300khz 14 20 ma load = 0a, v out = 1.8v, fsw = 600khz 29 41 ma i ddh 12v bias supply current shutdown (see note 1) 1.3 10 a inactive, no switching (see note 2) 6.5 20 a i recon specification a i current gain (i l to i sense )- 7 0 a < i l < 70a 95000 100000 105000 a/a temperature sensor specifications t range temperature sensor dynamic range 0 150 c a temp temperature sensor gain 3.01 mv/c ? temperature sensor voltage t j = 0c 832 mv protection features v dd_uvlo v dd uvlo threshold (rising) 1.47 1.57 1.64 v v dd uvlo threshold (falling) 1.41 1.5 1.58 v v ddh_ovlo v ddh ovlo threshold (rising) 15.48 16 16.41 v v ddh ovlo threshold (falling) 14.95 15.5 15.81 v v ddh_uvlo v ddh uvlo threshold (rising) 4.05 4.27 4.40 v v ddh uvlo threshold (falling) 3.90 4.09 4.25 v v bst_uvlo v bst uvlo threshold (rising) note 3 1.39 1.52 1.66 v v bst uvlo threshold (falling) note 3 1.32 1.45 1.57 v ocp peak positive ocp clamp level 59 67 80 a peak positive ocp clamp delay 63 ns peak positive ocp shutdown level 99 110 121 a peak positive ocp shutdown delay 42 ns peak negative ocp clamp level -79.1 -71.9 -64.7 a peak negative ocp delay 110 ns otp overtemperature shutdown rising threshold 140 150 165 c pwm inputv ih input voltage, high state v dd - 0.20 v v il input voltage, low state 0.20 v ? tristate control threshold (v in rising) 0.63 v ts_faultb input v ih ts_faultb digital threshold v ih 0.41 v v il ts_faultb digital threshold v il 0.17 v note 1: t sense , pwm and i sense pins of the slave are pulled low by the master. the sl ave is in this state before master oe is enabled. note 2: inactive, no switching: pwm signal is tristated by the master. the slave is in this mode when the master sheds a phase (tempora rily disabling this slave) to save power at lighter loads. note 3: v bst_uvlo is measured with respect to vx and not from ground. downloaded from: http:///
4 maxim integrated products, inc. vt1697sb typical operating characteristics master: t a = 25c; fsw = 600khz efficiency vs load current - 4 vt1697sb (vr12.0 ) i out (a) conditions: v in = 12v v bias = 1.8v inductor: clb1108-4-50tr-r system power dissipation - 4 vt1697sb (vr12.0 ) i out (a) conditions: v in = 12v v bias = 1.8v inductor: clb1108-4-50tr-r efficiency vs load current - 4 vt1697sb (vr12.5 ) i out (a) conditions: v in = 12v v bias = 1.8v inductor: clb1108-4-50tr-r system power dissipation - 4 vt1697sb (vr12.5 ) i out (a) conditions: v in = 12v v bias = 1.8v inductor: clb1108-4-50tr-r efficiency (%) 86% 88% 90% 92% 94% 96% 80% 82% 84% 0 20 40 60 80 100 120 140 160 180 v out = 0.8v v out = 1.0v v out = 1.1v v out = 1.2v v out = 1.35v v out = 1.5v system power dissipation (w) 15 20 25 30 35 40 0 5 10 0 20 40 60 80 100 120 140 160 180 v out = 0.8v v out = 0.9v v out = 1.1v v out = 1.2v v out = 1.35v v out = 1.5v efficiency (%) 90% 92% 94% 96% 86% 88% 0 20 40 60 80 100 120 140 160 180 v out = 1.6v v out = 1.8v v out = 1.7v v out = 1.9v v out = 2.0v system power dissipation (w) 15 20 25 30 35 40 45 0 5 10 0 20 40 60 80 100 120 140 160 180 v out = 1.6v v out = 1.7v v out = 1.8v v out = 1.9v v out = 2.0v downloaded from: http:///
5 maxim integrated products, inc. vt1697sb typical operating characteristics master: t a = 25c; fsw = 600khz vt1697sb 4-phase safe operating area (heatsink) v out (v) conditions: v in = 12v v bias = 1.8v inductor: cl1108-4-50tr-r vt1697sb 4-phase safe operating area (no heatsink) v out (v) conditions: v in = 12v v bias = 1.8v inductor: cl1108-4-50tr-r i out (a) 150 160 170 180 190 200 210 220 100 110 120 130 140 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 200lfm 55c 400lfm 25c 400lfm 70c 200lfm 25c 200lfm 70c 400lfm 55c no airflow 25c i out (a) 130 140 150 160 170 180 100 110 120 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 200lfm 25c 200lfm 55c 200lfm 70c 400lfm 25c 400lfm 55c 400lfm 70c no airflow 25c downloaded from: http:///
6 maxim integrated products, inc. vt1697sb pinout and block diagrams figure 2: vt1697sb pinout (qfn-16) pin information for vt169 7sb smart slave device v ddh (pin 1): 12v input supply voltage node. this node con- nects to the 12v input power supply source. high-frequency decoupling capacitors must be placed in close proximity to the slave ic on the same side as the vt1697sb. see table 2 for reference. v ss (pins 2-5): power switch ground node. these nodes normally connect directly to the ground plane. vx (pins 6-9): switching node. these nodes connect the switching node of the power devices to the output inductor. bst (pin 10): bootstrap supply for high-side drivers. v cc (pin 11): 1.8v supply for low-side drivers. v dd (pin 12): 1.8v supply for control circuits. pwm (pin 13): pwm input node. connect this node to the pwm output pin from the master. gnd (pin 14): ground for control circuits. i sense (pin 15): current sense output node. connect this node to the current sense input of the master through a sim- ple passive filter. ts_faultb (pin 16): temperature sense and fault output node. connect this node to the temperature sense pin of the master through a simple passive filter. 1 2 3 4 top view 5 6 9 10 7 8 v ddh v ss v ss v ss v ss 16 ts_faultb 15 i sense 14 gnd 13 pwm 12 v dd 11 v cc bst vx vxvx vx downloaded from: http:///
7 maxim integrated products, inc. vt1697sb pinout and block diagrams figure 3: ic block diagram bottom switch control/ fault logic current sense/ reconstruction level shift/ switch drivers temperat ure sense v dd uvlo vx short detect pwm ts_faultb vx i sense bst v cc v dd v ss v ddh v ddh ovlo/uvlo top s wit c h c boost uvlo ocp clamp level detect downloaded from: http:///
8 maxim integrated products, inc. vt1697sb theory of operation voltage regulation maxim smart slave ics provide the control logic, drivers, mon- itoring circuits and power semiconductors for a synchronous buck converter with fault protection, status monitoring and accurate lossless current sensing. phases are controlled by the master ic independently by separate phase control sig- nals. power switch control and drivers the smart slave ics operate in conjunction with a maxim master ic. the mast er controller will configure the voltage regulator based on its configuration resistors and the number of phases populated. the smart slave device?s switching is controlled by the proprietary command signals on the phase control lines. the phase control signal has three defined states: high, low and a "tri-state". "tri-state" is used for phase shedding and dcm modes. an external boost capacitor is required to supply the voltage for the high-side switch driver. vdd and vcc are brought out separately to allow separate decoupling to improve noise immunity on the vdd rail. current sense output the integrated lossless current sense (or ?current reconstruc- tion?) produces a precise ratiometric current sense signal for both positive and negative currents which is sent to the mas- ter as an analog current signal. this current sense technology provides accurate current information over load and tempera- ture that is not affected by tolerances of passive elements such as the output inductor, resistors and capacitors. phase configuration the ability for the master to dynamically disable and re- enable a phase is an integral part of the maxim master/slave architecture. the master sets the phase control signal to ?tri- state? to disable a phase. the same state is used to control dcm operation. when using a coupled inductor, a proprietary mode (coupled inductor mode) may be set by the master and communicated to the smart slave via the phase control signal to minimize losses due to coupled currents in inactive phases. protection circuits overcurrent protection the smart slave ics incorporate instantaneous overcurrent fault protection using the lossless current sense/reconstruc- tion. this overcurrent protection is separate from the system overcurrent protection, and is intended to operate only in extreme fault conditions to protect the ic and other compo- nents. the system overcurrent protection set by the master should be set with sufficient margin below the individual slave?s threshold to ensure correct system operation. for current sourcing operation, if the instantaneous current in the top switch (based on the current sense/reconstruction cir- cuit) exceeds the overcurrent protection value shown in the electrical characteristics tabl e, the slave will regulate the period of the top-side switch so as to keep its peak current at a safe level. the protection threshold has been set to ensure that the ic's maximum allowable peak current is not exceeded when using the recommended inductors. the sourcing cur- rent limiting is not considered a hard fault condition for slave, and therefore ts_faultb will no t be asserted. since clamp- ing is based on instantaneous reconstructed current, the rip- ple current must be considered when calculating the maximum average current per slave. the maximum average current before clamping can be calculated as shown in equation 1. note that the clamping is based on reconstructed current. limits shown in the electrical characteristics table for clamp level reflect expected variations in application condi- tions and external component characteristics. also note that the master (i.e., system) overcurrent protection should be set lower than the corresponding slaves' maximum operating cur- rent as stated above. equation 1 for current sinking protection, if the negative overcurrent pro- tection threshold is reached, the slave limits the current and ts_faultb is not asserted. the vt1697sb implements an additional ocp shutdown level (beyond the clamp levels). if the current in the top switch exceeds the ocp shutdown level (shown in the electrical characteristics table), the ic is turned off and fault is reported by asserting faultb pin. the slave is then latched off until the power is cycled. v dd and v boost undervoltage lockout the smart slave ics include undervoltage lockout circuits: v dd and v boost . for power sequencing guidelines and oper- ation with separate bias rails for master and slaves, please refer to appropriate master data sheet. v boost uvlo is active at all times after the initial system start up. it is not active during the initial system power on state (before regula- tion is enabled) and is activated approximately 20s after ini- tial start up. if either of these uvlo circuits is tripped during operation, the smart slave will st op switching and a fault sig- nal (ts_faultb pulled low) will be sent to the master. maximum average dc slave current ocp i ripple 2 ------------------- C = where, ocp = peak ocp clamp level (a) i ripple = peak-to-peak inductor ripple current (a) downloaded from: http:///
9 maxim integrated products, inc. vt1697sb theory of operation v in (v ddh ) undervoltage and overvoltage lockout the slaves include protection circuits that shut down the slave and assert ts_faultb if v ddh is above or below the correct operating range. if either of these circuits is tripped during operation, the slave will stop switching and a fault signal (ts_faultb pulled low) will be sent to the master. temperature sensing and overtemperature protection each smart slave ic incorporates an accurate die tempera- ture sensor. the temperature sense signal is sent to the mas- ter as an analog signal via the temperature sense pin. the actual temperature of each smart slave device is then made available via the smbus of the master. the smart slave ic also includes overtemperature protection. if the trip point is reached, the ic immediately shuts down and the fault is reported to the master via the ts_faultb pin. vx short protection the smart slave ics include a vx short detection to detect a local short circuit from the vx node to either v ddh or ground. if such a fault is detected, the slave shuts down and commu- nicates a fault to the master via the ts_faultb pin. ts_faultb signal if a fault is detected, the smart slave sends a signal to the master by pulling the ts_faultb pin to ground. under nor- mal conditions, this pin is used to send an accurate analog representation of the slave temperature. if a fault is detected, this pin is asserted low to indicate that a fault condition was detected by a slave ic. table 1 shows the faults that result in this signal being asserted. for a latching fault, the fault must be cleared and the v dd power cycled to re-enable the ic (for non-latching faults, see note below the table 1.). please refer to the applicable master ic data sheet for details about han- table 1: fault detection and protection circuits fault description type fault flag (ts_faultb) boost uvlo undervoltage lockout on boost supply shutdown * asserted v ddh uvlo undervoltage lockout on v ddh shutdown * asserted v ddh ovlo overvoltage lockout signal on v ddh shutdown * asserted v dd uvlo undervoltage lockout signal on v dd shutdown * asserted v x short vx short-to-ground or v ddh shutdown asserted pocp (sourcing) positive/sourcin g overcurrent protection cycle-by-cycle current limit not asserted nocp (sinking) negative/sinking overcurrent prot ection cycle-by-cycle current limit not asserted otp overtemperature protection shutdown asserted * vddh_uvlo, vddh_ovlo, vbst_uvlo and vdd_uvlo are non-latching faults. if a non-latching fault is detected by the slave, it wi ll assert ts_faultb signal low and stop switching. the slave resumes switching and de- asserts ts_faultb around 37s from when the fault condition i s removed. please refer to the master data sheet for master response to ts_faultb asserted low by the slave device. downloaded from: http:///
10 maxim integrated products, inc. vt1697sb theory of operation design considerations phase current sharing and steering control maxim master/slave chipsets offer options for thermal balanc- ing in applications where one or more phases have different thermal characteristics. the current sense and chipset regu- lation system offer the potential for current steering, where a percentage of current can be steered away from any phase, allowing that phase to operate at a different current than the other phases. this allows a precise scaling of current in any slave(s) to achieve proper thermal balance between phases. refer to the applicable maxim master ic datasheet for more information on how to program this feature. thermal path and printed circuit board design the smart slave ic has an exposed pad on the top-side of the package that is designed as an additional thermal path. this pad is electrically connected to a gnd /v ss , but is not intended for use as an electrical con nection. since there is normally sufficient airflow above the regulator, conducting heat from the top of the package results in a low junction-to-ambient thermal impedance, and hence lower junction temperature. this method provides additional thermal path to the heat flow from the die to the pcb to ambient and also reduces the tem- perature of the pcb. thermal performance is presented for various thermal conditions and airflow rates in the soa plots. printed circuit board (pcb) layout pcb layout can significantly affect the performance of the reg- ulator. careful attention should be paid to the location of the input capacitors and the output inductor which should be placed close to the ic. the vx traces include large voltage swings (greater than 12v) with dv/dt greater than 10v/ns. it is recommended that these traces are not only kept short, but also are shielded with a ground plane immediately beneath. gerber files with layout information and complete reference designs can be obtained by contacting a maxim account rep- resentative. please contact maxim to obtain qfn layout guidelines for optimal design. table 2: typical boost, filtering and decoupling capacitor requirements description value type package qty v dd capacitor 0.1 ? f/6.3v x7r/125c 0603 1 v cc capacitor 1 ? f/6.3v x7r/125c 0603 1 boost capacitor 0.22 ? f/6.3v x7r/125c 0402 1 v dd r filter 10 ? 1/16w 1% 0402 1 v ddh hf capacitor 1 1 ? f/16v x7r/125c 0603 2 v ddh hf capacitor 1 0.1 ? f/16v x7r/125c 0402 2 v ddh bulk capacitor 2 10 ? f/16v x5r 0805/1206 2 note 1: all v ddh high-frequency capacitors must be placed in close proximity to the slave ic and on the same side of the pcb as the slave ic. please refer to maxim's layout guideline for component placement requirements and rec- ommendations. note 2: for operation below 10.8v, two 22 ? f bulk capacitor are recom- mended instead of two 10 ? f capacitors. note 3: v cc should be directly connected to bias supply. downloaded from: http:///
vt1697sb 11 maxim integrated products, inc. package dimensions packa g e outl i ne - 16 lead qfn [type g] title: doc no. re. e s ap-2 8 96 0 pa g e 1 of 3 downloaded from: http:///
vt1697sb 12 maxim integrated products, inc. package dimensions title: doc no. re. e s ap-2 8 96 0 pa g e 2 of 3 packa g e outl i ne - 16 lead qfn [type g] downloaded from: http:///
vt1697sb 13 maxim integrated products, inc. revision history revision history for pricing, delivery, and ordering information, please contact maxim direct at 1-888 -629-4642, or visit maxim integrated?s website at www.maximintegrated.com. maxim integrated cannot a ssume responsibility for use of any circuitry other th an circuitry entirely em bodied in a maxim inte- grated product. no circuit patent licenses are implied. maxim inte grated reserves the right to change the circuitry and specifi ca- tions without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics tabl e are guaranteed. other parametric values quoted in this data sheet are provided for guidan ce. maxim integrated and the maxim integrated logo are trade- marks of maxim integrated products, inc. ? 2014 maxim integrated products, inc. revision description date 0 initial data sheet n/a 1 changed status of vt1697sb to new product. updated i cc + i dd , v bst_uvlo and nocp specifications in the electrical characteristics table. made a change in the ?filter? (from v ddh to v dd ) in table 2. 1/14 2 updated to maxim template 2/14 3 updated electrical characteristics table and overcurrent protection section. updated operating current rating to 55a. removed all vt1677sb references from data sheet. 9/14 4 removed ?scalable 120a multiphase solution in < 835mm 2 ? in features and benefits section 11/14 downloaded from: http:///

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